CCSDS 124.0-B-1 telemetry compression
Verified compression for flight and ground systems
Data compression for spacecraft housekeeping telemetry that is verified against the official CCSDS cross-validation dataset: synthesizable VHDL IP cores for FPGA and ASIC workflows, plus a companion C++ package for reference, integration, and ground-segment use.
Validation first, implementation second
Our implementation targets missions where compression behavior must be predictable, portable, and traceable to the final CCSDS standard and official cross-validation evidence.
Verified CCSDS behavior
The VHDL compressor is fully cross-validated against the official CCSDS dataset and supported by compliance, verification, and acceptance documentation.
Flight IP delivery
The hardware package is technology-independent VHDL RTL, intended for integration into FPGA, ASIC, and custom memory workflows.
Software counterpart
The C++17 implementation supports software-side integration, reference use, and ground processing around the same POCKET+ telemetry compression domain.
Technical highlights
VHDL IP core
The FPGA package keeps the compressor core separate from implementation-specific memories, making it practical to adapt the same RTL to the selected target device, RAM macros, and system integration rules.
| Standard target | CCSDS 124.0-B-1 (POCKET+) housekeeping telemetry compression. |
|---|---|
| Top-level core | Compressor RTL with explicit start, ready, busy, finished, and fault interfaces. |
| Memory model | External input, initial-mask, and compressed-output RAM interfaces with configurable read latency. |
| Validation tooling | GHDL simulation, fault-code tests, cross-validation generation, sizing tools, portability checks, and release evidence scripts. |
| Integration boundary | Replaceable RAM wrapper for target-specific memory macros while preserving the documented contract. |
What the product package covers
PocketPlus is delivered as engineering IP, not as a black-box demo. The package is meant to support design review, integration, regression, and mission-specific sizing.
RTL and memory wrapper
- Synthesizable compressor core.
- Technology-independent RAM wrapper.
- Configurable word width, input bound, output pointer width, and RAM latency.
Verification evidence
- Official CCSDS cross-validation dataset workflow.
- Fault-code and handshake simulation.
- Performance logging and acceptance procedure.
Integration documentation
- Compliance matrix and verification report.
- Memory-interface and portability guidance.
- Sizing model for mission-specific configurations.
Where it fits
Spacecraft housekeeping telemetry
Compress fixed-length telemetry vectors before downlink while retaining standards-focused behavior.
Onboard data handling
Integrate compression into FPGA or ASIC telemetry-processing pipelines with explicit RAM contracts.
Ground and test systems
Use the C++ package and validation tooling to support reference checks, test data, and operational integration.
Bring telemetry compression into your mission architecture
Contact us for licensing, FPGA integration support, cross-validation evidence, mission-profile sizing, and software-side deployment options.
PocketPlusVHDL is focused on CCSDS 124.0-B-1 compressor behavior. Decompression, mission packet framing, target-specific timing closure, and architecture-specific RAM implementation are handled as integration activities.
